1. Technical Field
The invention relates to a gate controlled fin resistance element for use as electrostatic discharges (ESD) protection element in an electrical circuit, and to a device for protection against electrostatic discharges in an electrical circuit.
2. Description of the Related Art
The development of efficient protection mechanisms for protecting an electronic component against ESD constitutes a growing challenge, particularly when using advanced process technologies such as, for example, MuGFET technologies or FinFET technologies, in view of the ever shrinking dimensions of the electronic devices and the associated increasing sensitivity toward electrical overvoltages.
Electrostatic discharges (ESD) represent a permanent threat to integrated circuits (IC). During an ESD event, short electrical discharge pulses occur during which high electric currents flow or high electrical voltages occur which can damage one or more electronic components of the circuit. Therefore, protection against electrostatic discharges or ESD events is necessary. Multigate field effect transistors (MuGFET) or fin field effect transistors (FinFET), that is to say field effect transistors having a fin structure, constitute one technological option for further developing CMOS circuits (complementary metal oxide semiconductor) even as far as the 32 nm technology node (32 nm node) and beyond.
FIG. 1A shows a conventional FinFET structure 100, that is to say a field effect transistor having a fin structure. The FinFET structure has a gate 104 “wound” around a free-standing silicon fin 102. Two source/drain regions 103 are formed in the fin 102. If only the two sidewalls of the fin 102 are covered with a thin gate oxide layer and are controlled by the gate 104, this is designated as a FinFET structure or else double gate FinFET structure. If, in addition to the two side areas, further sides of the fin 102 (e.g. upper and/or lower face) are covered with the thin gate oxide layer and are likewise controlled by the gate 104, it is designated as a multigate FET structure (MuGFET structure). If three sides of the fin are controlled by the gate 104, this is also designated as a triple gate structure or a trigate structure. The fin 102 is insulated from a silicon substrate 101 by a buried oxide layer 105 (BOX).
FIG. 1B shows for comparison a conventional planar n conducting FDSOI field effect transistor 150 (Fully Depleted Silicon On Insulator NFET), enclosed in a very thin silicon layer (few nm). The silicon layer is formed on a buried silicon dioxide layer 152, which silicon dioxide layer 152 is in turn formed on a silicon substrate 151. The NFET 150 shown in FIG. 1B has heavily n doped diffusion regions 154, so-called raised source/drain regions 156, a p doped well region 155, a gate region 157 and also isolation regions 153 (Shallow Trench Isolation, STI).
Advantages of multigate field effect transistors or fin field effect transistors are a low leakage current and a small parasitic capacitance, for example, which are comparable with those of FDSOI elements, but in contrast to SOI elements there is no need to form an extremely thin perfect silicon layer on the buried oxide layer. This significantly reduces costs for the substrates.
MuGFETs or FinFETs react extremely sensitively to ESD discharges on account of their small volume exposed to a high power during the discharge. The fin structure results for example in a poor thermal conduction of the devices, which leads to an extremely high intrinsic susceptibility. To express it clearly, during an ESD discharge during which a high current flows through the fin, the poor heat dissipation means that severe heating of the fin structure can occur, which may lead to burn-out of the fin.
The development of effective ESD protection elements in FinFET technologies or MuGFET technologies constitutes a major technological challenge. One problem consists in achieving a uniform distribution of the electric current over the entire width of the transistor in order thereby to minimize the power loss per fin. The possibility of increasing the load resistance (ballasting resistance) of the transistor by means of extending the drain region is restricted, however, by the maximum fin length permitted in the fabrication process. Salicide blocking, as employed in planar technologies, may in turn lead to process problems at the perpendicular sidewalls of the fin.
Many ESD protection elements such as are known from planar bulk technologies can no longer be used in MuGFET technologies or FinFET technologies. By way of example, vertical devices are not available on account of the lacking bulk, and diodes can only be realized as gate-bound lateral diodes. Low voltage thyristors (Low Voltage Silicon Controlled Resistor, LVSCR) also cannot be implemented in a known manner.
In many cases, planar PD devices (partially depleted, that is to say partially depleted of charge carriers) can be integrated together with MuGFETs and FinFETs in one process, thereby making it possible to use the known types of protection elements. One disadvantage of this method, however, is that the breakdown conditions and trigger conditions of planar protection elements and FinFETs (MuGFETs) are not coordinated with one another, which leads to inadequate protection against ESD events. A further disadvantage of this method is that the use of a second device type that differs greatly compared with the standard driver transistor may lead to an increase in the process complexity.
In order to achieve a uniform current conduction in the individual fins themselves, there is the possibility of connecting small polysilicon resistors in series. However, one disadvantage of this method is that the area requirement of the transistor is thereby significantly increased.